Add in that 1 or their two attacks is via SMT, I think ASi is probably pretty safe from this. I won't say this attack is impossible on Apple Silicon but as you say, it would be more difficult-probably much more difficult. That complexity isn't there in the M1 or any Arm RISC system. I was reading as much of the white paper as I could understand without doing further research and my conclusion is that even if the M1 is using a micro-op cache, the authors are using the x86 ISA complexity as a way of detecting micro-op cache hits and misses. This is also one of the main reasons M1 has such amazing single threaded performance since it isn’t limited by the decoder. The x86 ISA should die already. Micro-ops are fixed length and shouldn’t require much caching unlike Intel/AMD. The memory model of ARM makes these types of attacks more difficult. ![]() Spectre and Meltdown are not singular flawsthey individually represent a class of closely-related. Since Apple's ARM SoC cores don't use SMT, it looks like they are safe from this. Meltdown is a vulnerability allowing a process to read all memory in a given system. Someone with more knowledge of Arm CPU Architecture should chime in.Įdit: And apparently SMT (also known as hyper-threading) is involved. Intels legal woes surrounding the Meltdown and Spectre vulnerabilities in its processors are increasing, with more legal firms filing class action suits against the chip company, this time on the. In general RISC CPUs have much simpler decoding so it is possible that micro-ops aren't cached at all or the cache structure is much simpler. ![]() ![]() The caching of micro-ops is the source of this vulnerability. I know that Apple's Arm CPUs use micro-ops but I don't know anything about if or how they are cached.
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